View AK1590_7820334.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak15 90 ] ms1478 - e - 01 1 20 13 / 2 AK1590 1g hz delta - sigma fractional - n frequency synthesizer 1. overview ak 1590 is a delta - sigma fractional - n pll (phase locked loop) frequency synthesizer with a frequency switching function, covering a w ide range of fre quencies from 60 to 1000 mhz. this product consists of an 18 - bit delta - sigma modulator, a low - noise phase frequency comparator, a highly accurate charge pump, a reference divider, dual - modul e prescaler (p/p+1) and frequency offset adjustabl e circuits. 2. feat ures ? operating frequency: 60 to 1000 mhz ? programmable charge pump current: in a normal operating scheme, the charge pump current can be set in 8 steps, in the range from 20 to 16 8 a. in a fast lockup scheme, the charge pump current can be set in 8 steps, in the range from 0.8 to 2 .3m a. ? supply voltage: 2 .7 to 5.5 v (pvdd pin ) ? separate power supply for the charge pump: pvdd to 5.5v (cpvdd pin) ? on - chip power - saving features ? fre quency o ffset adjustable function : no glitch operation for afc (automatic frequency control) and dfm (digital frequency modulation) ; when the offse t adjustable register is accessed, int and num are recalculated internally. ? ge neral - purpose output: t wo gen eral - purpose output po rts to control peripheral parts ? l ow phase noise: - 20 1 dbc/hz ? l ow consumption current: 2.5 ma typ ? package: 24pin qfn ( 0.5mm pitch , 4mm ? 4mm ? 0.7 mm) ? operating temperature: - 40 to +85 c
[ak15 90 ] ms1478 - e - 01 2 20 13 / 2 table of contents 1. overview ________________________________ ________________________________ ___________ 1 2. features ________________________________ ________________________________ ___________ 1 3. block diagram ________________________________ ________________________________ ______ 3 4. pin functional description ________________________________ ____________________________ 4 5. absolute maximum ratings ________________________________ ___________________________ 6 6. recommended operating range ________________________________ _______________________ 6 7. electrical characteristics ________________________________ ______________________________ 7 8. block functional descriptions ________________________________ ________________________ 11 9. register map ________________________________ ________________________________ _______ 20 10. register functional description ________________________________ _______________________ 21 11. ic interface schematic ________________________________ _______________________________ 27 12. recommended connection schematic for off - chip components ___________________________ 29 13. power - up sequence ________________________________ ________________________________ _ 31 14. typical evaluation boar d schematic ________________________________ ___________________ 32 15. block diagram by power supply ________________________________ _______________________ 33 16. outer dimensions ________________________________ ________________________________ ___ 34 17. marking ________________________________ ________________________________ ___________ 35 in this specification, the following notations are used for specific signal and register names: [name] : pin name : register group name (address name) { name} : register bit name
[ak15 90 ] ms1478 - e - 01 3 20 13 / 2 3. block diagram fig. 1 block diagram charge pump 2 (for fast lock up) cp cpz phase freqency detector refin + - prescaler 4/5, 8/9,16/17 pulse swallow counter lock detect rfinp rfinn swin cpvdd cpvss pvdd vref dvss pvss ld ? 18bit clk data le register 24bit n divider fast counter 13bit gpo1 test2 test1 ldo test3 gpo2 r counter 8bit bias charge pump 1 pdn1 pdn2 num offset + int s um
[ak15 90 ] ms1478 - e - 01 4 20 13 / 2 4. pin functional description table 1 pin function no. n ame i/o pin functions power down remarks 1 cpvdd p power supply for charge pump 2 test 3 di test pin 3 . this pin must be connected to ground. internal pull - down, schmidt trigger input 3 test1 di test pin 1 . this pin must be connected to ground. internal pull - down, schmidt trigger input 4 le di load enable schmidt trigger input 5 data di seria l data input schmidt trigger input 6 clk di serial clock schmidt trigger input 7 ld do lock detect low 8 pdn2 di power down pin for pll schmidt trigger input 9 pdn1 di power down signal for ldo schmidt trigger input 10 refin ai reference input 11 test2 di test pin 2 . this pin must be connected to ground. internal pull - down, schmidt trigger input 12 gpo1 do general - purpose output pin 1 low 13 gpo2 do general - purpose output pin 2 low 14 dvss g digital ground pin 15 vref aio connect to l do reference voltage capacitor low 16 rfinn ai prescaler input 17 rfinp ai prescaler input 18 pvdd p power supply for peripherals 19 bias aio resistance pin for setting charge pump output current 20 pvss g ground pin for peripherals 21 cp ao charge pump output hi - z 22 cpz aio connect to the loop filter capacitor note 1 , note 2 23 swin ai connect to resistance pin for fast lockup note 1 , note 2 24 cpvss g ground pin for charge pump note 1) for detailed functional descriptions, see the section charge pump and loop filter in 8 . block functional description below. note 2) the input voltage from [ cpz ] pin is used in the internal circuit. [ cpz ] pin must not be open even when the fast lock up feature is unused. for the output destination from [ cpz ] pin, see fig.5 loop filter schematic. [ swin ] pin could be open when the fast lockup feature is not used. the state of loop filter switch is on when [ pdn1]= low, [pdn2]= low or [pdn1]= high, [ pdn2]= low . note 3) power down mean s the state where [pdn1]=[pdn2]=low after power on. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin
[ak15 90 ] ms1478 - e - 01 5 20 13 / 2 fig . 2 package pin layout 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 top view 23 24 22 21 cpvdd test3 test1 data le clk ld pdn2 pdn1 refin test2 gp o1 gpo2 dvss vref rfinn rfinp pvdd bias pvss cp cpz swin cpvss
[ak15 90 ] ms1478 - e - 01 6 20 13 / 2 5. absolute maximum ratings table 2 absolute maximum ratings parameter symbol min. max. unit remarks supply voltage vdd1 - 0.3 6.5 v note 1, note 2 vdd2 - 0.3 6.5 v note 1, note 3 gr ound level vss1 0 0 v voltage ground level , note 4 vss2 0 0 v voltage ground level , note 5 vss3 0 0 v voltage ground level , note 6 analog input voltage vain1 vss1 - 0.3 vdd1+0.3 v note 1, note 7, note 10 vain2 vss2 - 0.3 vdd2+0.3 v note 1, note 8, note 10 digital input voltage vdin vss3 - 0.3 vdd1+0.3 v note 1, note 9, note 10 input current iin - 10 10 ma storage temperature tstg - 55 125 c note 1) 0v reference for all voltages. note 2) applied to [pvdd] pin . note 3 ) applied to [ c pvdd] pin note 4 ) a pplied to [pvss] pin . note 5) a pplied to [cpvss] pin . note 6 ) a pplied to [ d vss] pin . note 7 ) applied to [ refin ] , [ rfinn ] and [ rfinp ] pins. note 8 ) applied to [ cpz ] and [ swin ] pins. note 9 ) ap plied to [ clk ] , [ data ] , [ le ] , [ pdn1 ] and [ pdn2 ] pins. no te 10 ) maximum must not be over 6.5v. exceeding these maximum ratings may result in damage to ak 1590 . normal operation is not guaranteed at these extremes. 6. recommended operating range table 3 recommended operating range param eter symbol min. typ. max. unit remarks operating temperature ta - 40 85 ? c supply voltage vdd1 2.7 3.3 5.5 v applied to [ pvdd ] pin vdd2 vdd1 5.0 5.5 v applied to [ cpvdd ] pin vdd1 and vdd2 can be driven individually within the recommended o perating range. the specifications are applicable within the recommended operating range (supply voltage / operating temperature).
[ak15 90 ] ms1478 - e - 01 7 20 13 / 2 7. electrical characteristics 1. digital dc characteristics table 4 digital dc characteristics param eter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8 ? vdd1 v note 1 low level input voltage vil 0.2 ? vdd1 v note 1 high level input current iih vih = vdd1 = 5.5v - 1 1 ? a note 1 low level input current iil vil = 0v, vdd1 = 5.5v - 1 1 ? a note 1 high level output voltage voh ioh = - 500 ? a vdd1 - 0.4 v note 2 low level output voltage vol iol = 500 ? a 0.4 v note 2 note 1) applied to [ clk ] , [ data ] , [ le ] , [ pdn1 ] and [ pdn2 ] pins. note 2 ) applied to [ ld ] , [gpo1] and [gp o2] pin s .
[ak15 90 ] ms1478 - e - 01 8 20 13 / 2 2. serial interface timing fig. 3 serial interface timing chart table 5 serial interface timing parameter symbol min. typ. max. unit remarks clock l level hold time tcl 40 ns clock h level hold time tch 40 ns clock setup time tcsu 20 ns data setup time tsu 20 ns data hold time thd 20 ns le setup time tlesu 20 ns le pulse width tle 40 ns note 1 ) while [ le ] pin is setting at low, 24 iter ation clocks have to be set with [ clk ] pin. i f 25 or more clocks are set, the last 24 clocks synchronized data are valid. note 2 ) offset register must be written at the lower speed than calculated frequency by 1/3.5 ? rf frequency /(int+7) . if the writi ng speed is f aster than this, the setting is in valid. le (input) clk (input) data (input) tsu thd tcsu d19 d18 d0 a0 a1 a2 a3 tch t cl tlesu tle d19
[ak15 90 ] ms1478 - e - 01 9 20 13 / 2 3. analog circuit characteristics the resistance of 27k? is connected to [ bias ] pin, vdd1 = 2.7v to 5.5v, vdd2 = vdd1 to 5.5v, C 40c ta 85c parameter min. typ. max. unit remarks rf characterist ics input sensitivity - 10 +5 dbm input frequency 60 500 mhz prescaler 4/5 60 1000 mhz prescaler 8/9,16/17 refin characteristics input sensitivity 0.4 2 vpp input frequency 5 40 mhz prescaler maximum allowable prescaler output frequency 1 25 mhz phase detector phase detector frequency 5 mhz charge pump charge pump 1 maximum current 16 8.9 ? ? vcpo vdd2 0.5 vcpo vdd2 regulator vref rise time 50 ? current consumption idd1 1 0 ? [pdn1]=low, [pdn2]=low" [pdn1]=high, [pdn2]=high [pdn1]=high, [pdn2]=high [pdn1]= , [pdn2]=low" see fig. 4 charge pump characteristics - voltage vs. current: icp vs. vcpo: [{1/2(|i1| - |i2|)}/{1/2(|i1|+|i2|)}]100 [%]
[ak15 90 ] ms1478 - e - 01 10 20 13 / 2 note 3 ) idd 3 is the curre nt that consumes constantly at [cpvdd]. this d oes not include the operation current in f ast l ockup mode. note 4 ) when both [pdn1] and [pdn2] are high , the total current consumption is equivalent to idd2+idd3 . note 5 ) in the shipment test, the exposed pad on the center of the back of package is connected to ground. resistance connected to bias pin for setting charge pump output current parameter min. typ. max. unit remarks bias resistance 22 27 33 k? fig. 4 charge pump characteristics - voltage vs. current isink isource vcpo icp vdd2 - 0.5 vdd2/2 0.5 i1 i1 i2 i2
[ak15 90 ] ms1478 - e - 01 11 20 13 / 2 8. block functional descriptions 1. frequency setup ak 1590 is a fractional - n type synthesizer that takes 2 18 as the denominator, which calculates the integer and numerator to be set using the follo wing formulas: frequency setting = f pfd (integer + numerator / 2 18 ) integer = round (target frequency / f pfd ) numerator = round {(target frequency C pfd ) / ( f pfd / 2 18 )} note) round: rou nded off to the nearest integer f pfd : phase frequency detector comparative frequency ( = [refin] input frequency / r divider ratio) ? calculation examples example 1) the numerator is positive ; when the target frequency is 950 .0375mhz and f pfd is 1mhz. integer = 950 .0375mhz / 1mhz = 950 .0375 it is rounded off to 950 (decimal) = 3b6 (hexadecimal) = 0011 1011 0110 (binary) numerator = ( 950 .0375mhz - 950 1mhz) / (1mhz / 2 18 ) = 9830.4 it is rounded off to 9830 (decimal) = 2666 (hexadecimal) = 10 0110 0110 0110 (binary) frequency setting =1mhz ( 950 + 9830 / 2 18 ) = 950 .0374985mhz (in this case the frequency error is 1.5hz.) example 2 ) the numerator is negative ; when the target frequency is 950.550mhz and f pfd is 1mhz. integer = 950.550mhz / 1mhz = 950.550 it is rounded off to 951 (decimal) = 3b7 (hexadecimal) = 0011 1011 0111 (binary) numerator = (950.550mhz - 951 1mhz) / (1mhz / 2 18 ) = - 117964.8 it is rounded off to - 117965 (decimal), which is r educed from 2 18 to be converted into binary for 2's complementary expression. 2 18 - 117965 (decimal) = 144179 (deci mal) = 23333 (hexadecimal) = 10 0011 0011 0011 0011 (binary) frequency setting =1mhz (951 + ( - 117965/2 18 )) = 950.5499992mhz (in this case the frequency error is 0.8hz.) ? calculation of 2s complement representation 1) positive number: binary expression (u nmanipulated) exp. 100 (decimal) 64 (hexadecimal) = 110 0100 (binary) 2) negative number: 2 18 minus this number in binary expression exp. C 100 (decimal) 2 18 - 100 = 262044 (decimal) = 3ff9c (hexadecimal) = 11 1111 1111 1001 1100 (binary)
[ak15 90 ] ms1478 - e - 01 12 20 13 / 2 2. frequen cy offset a djust ment AK1590 has an offset adjustable register which can tune the carrier frequency set by {num[17:0]} in

and {int[14:0]} in

. when t he offset register : {ofst[17:0]} in

is accessed, {num[17:0]} a nd {int[14:0]} are internally recalculated automatically and their recalculated data are us ed in delta - sigma and n - divider. this operation is suitable for afc and dfm applications. when frequency offset is not used, the offset register must be written 00000 (hexadecimal ). ? setting examples example 1) the frequency offset is positive ; when the frequency offset is 100hz and f pfd is 1mhz. frequency offset = 100hz / ( 1mhz/2 18 ) = 26.2 it is round off to 26 (decimal) = 1a (hexadecimal) = 11010 (binary) example 2 ) the frequen cy offset is negative ; when the frequency offset is - 100hz and f pfd is 1mhz. frequency offset = - 100hz / ( 1mhz/2 18 ) = - 26.2 it is round off to - 26 (decimal), which is r educed from 2 18 to be converted into binary for 2s complementary expression. 2 18 C 26 = 262118 (decimal) = 3ffe6 (hexadecimal) = 11 1111 1111 1110 0110 (binary) ? algorithm of recalculation int written data in integer register {int[14:0]} num written data in numerator register {num[17:0]} ofst written data in offset regi ster {ofst[17:0]} int_recal recalculated integer data num_recal recalculated numerator data sum = num + ofst sum ? 0.5 num _ recal = (num + ofst) - 1 int _ recal = int + 1 sum < - 0.5 num _ recal = (num + ofst) + 1 int _ recal = int - 1 num _ recal = num + ofst int _ recal = int yes yes no no
[ak15 90 ] ms1478 - e - 01 13 20 13 / 2 3 . charge pump and loop filter ak 1590 has two charge pumps; charge pump 1 for normal operation and charge pump 2 for fast lockup mode . the inte rnal timer is use d to switch th e se two charge pumps to achieve a fast l ock pll. the loop filter is external and connected to [ cp ] , [ swin ] and [ cpz ] pins. [ cpz ] pin should be connected to r2 and c2 , which are intermediate nodes, even if the fast lockup is not used. theref ore, r2 must be connected to [ cp ] pin, while c2 must be connected to the ground. r2 and r2 are connected in parallel with internal switch in fast lockup. these r2 and r2 parallel resistance value is required for calculating loop bandwidth and phase margi n in fast lockup operation . fig. 5 loop filter schematic c2 phase detector up down timer vco loop filter c1 c3 r2 r2' r3 cp cpz swin
[ak15 90 ] ms1478 - e - 01 14 20 13 / 2 4 . fast lockup mode setting d[16] = { fasten } in to 1 enabl es the fast lock u p mode for ak 1590 . changing a frequency setting (the frequen cy change s at the rising edge of [ le ], when and are accessed. ) or [pdn2] pin is turned from low to high with {fasten}=1 enables the fast lockup mode. the loop filter switch turns on during the timer period specified by the counter value in d[12:0] = { fast[12:0] } in , and the charge pump for the fast lockup mode (charge pump 2) is enabled. after the timer period elapsed, the loop filter switch turns off . t he charge pump for normal operation (charge pump 1) is enabled . d[12 :0] = { fast[12:0] } in is used to set the timer period for this mode. the following formula is used to calculate the time period: phase detector frequency cycle counter value set in { fast[12:0] } the charge pump current can be adjusted with the register setting in 8 steps in normal operation (charge pump 1) and 8 steps in the fast lockup operation (charge pump 2). the charge pump current for normal operation (charge pump 1) is determined by the setting in { c p1[2 :0] } , which is a 3 - bit address of d[17 :15] in , and a value of the resistance connected to [ bias ] pin. the following formula s show the relationship between the resistance value, the register setting and the current. charge pump 1 m inimum current (cp1_min) = 0.57 / resistance connected to [ bias ] pin charge pump 1 current = cp1_min ( {cp1[2:0]} + 1) the charge pump current for the fast lockup mode operation (charge pump 2 current) is determined by the setting in { cp2[2:0] } , which is a 3 - bit address of d[15:13] in , and a value of the resistance connected to [ bias ] pin . the following formula s show the relationship between the resistance v alue, the register setting and the current . charge pump 2 minimum current (cp2_min) = 5.7 / resistance conne cted to [ bias ] pin cha rge pump 2 current = cp2_min ( {cp2[2:0]} + 4) the allowed range for the resistance ( connected to [ bias ] pin ) i s from 22 to 33 k? for both normal and fast lockup mode operations. for details of current settings, see 10 . register functional description. fig. 6 timing chart for fast lo ckup mode fast lockup mode charge p ump 2 on normal normal charge p ump 1 off charge p ump 1 off f a st l ockup time specified by the timer operation mode charge pump l o op filter switch the frequency change s or [pdn2] pin is set from low to high during d[16] = {fsten} in < address4 > is set to 1 .
[ak15 90 ] ms1478 - e - 01 15 20 13 / 2 5 . lock detect (ld) signal in ak 1590 , lock detect output can be selected by d[11] = { ld } in . when d[11] is set to 1" , t he phase detector output provides a phase detection status as an analog level (comparison result) . th is is call ed a nalog l ock d etect . when d[11] is set t o 0, the lock detect signal output s a ccording to the on - chip logic. this is called d igital l ock d etect . 5 .1 analog lock detect in analog lock detect, the phase detector output comes from [ ld ] pin. fig. 7 analog lock detect operation reference clock pfd clock vco divide clock phase detector output ld output
[ak15 90 ] ms1478 - e - 01 16 20 13 / 2 5 .2 digital lock detect in digital lock detect, [ld] pin outputs low whe n the frequency is set. the output of [ld] pin turns from low to high (which means locked state ) when a phase error smaller than t is detected for 63 times consecutively. if the phase error that is larger than t is detected for 63 times consecutively during [ld] pin outputs high , t he output of [ld] pin turns to low(which means unlocked state ). the accuracy of the phase detect is set by {ldcksel[1:0]} . {ldcksel[1:0]} is set to 0 0 : t = refin cycle (this is not available for the reference dividing ratio 3 .) {ldcksel[1:0]} is set to 0 1 : t = refin cycle 2 (this is not available for the r eference dividing ratio 5.) {ldcksel[1:0]} is set to 10 : t = refin cycle 3 (this is not available for the reference dividing ratio 6.) since AK1590 is a delta - sigma fractional - n type, a phase error up to 7 times larger than the vco period frequenc y may occur in the phase detector. therefore {ldcksel[1:0]} setting should be large enough to cover the amplitude of the delta - sigma fractional frequency. however, if the vco frequency does not satisfy either of the following formula, the digital lock dete ct is not available . in such case, the analog lock detect should be used. {dith} = d [ 14 ] in is set to 1 (dith on) : vco frequency > [refin] pin input frequency / [ {ldcksel[1:0]} + 1] 7 {dith} = d [ 14 ] in is set to 0 (dith off) : vco frequency > [refin] pin input frequency / [ {ldcksel[1:0]} + 1] 4 example 1) when [refin] input frequency = 33.6mhz, {dith} = 1, {ldcksel[1:0]} = 10 ; 33.6mhz / (2+1) 7 = 78.4mhz as a result, the digital lock detect is not available if the vco frequency is equivalent to or smaller than 78.4mhz. example 2) when [refin] inpu t frequency = 33.6mhz, {dith} = 0, {ldcksel[1:0]} = 0 1 ; 33.6mhz / (1+1) 4 = 67.2mhz as a result, the digital lock detect is not available if the vco frequency is equivale nt to or smaller than 67.2mhz.
[ak15 90 ] ms1478 - e - 01 17 20 13 / 2 ? setup example { dith } = d [ 14 ] in is set to 1 (dith on) : digital lock detect available digital lock detect unavailable vco frequency 180mhz 70mhz [refin] input frequency 12.8mhz 32mhz {ldcksel[1:0]} 0 (dith off) : digital lock detect available digital lock detect unavailable vco frequency 180mhz 60mhz [refin] input frequency 1 2.8mhz 32mhz {ldcksel[1:0]} fig. 8 digital lock detect operation invalid invalid reference clock pfd clock vco divide clock phase detector output valid valid valid invalid valid case: { ld c ksel} = 0 0 l ock detect result
[ak15 90 ] ms1478 - e - 01 18 20 13 / 2 fig. 9 transition flow chart: unlock ed state to lock ed state fig. 10 transition flow chart: lock ed state to unlock ed state phase error < t flag = flag+1 lock ed ([ld]= hi gh ) unlock ed ([ld]= low ) yes no flag > 63 flag = 0 yes no phase error > t yes flag = 0 flag = flag+1 flag > 63 no yes unlock ed ([ld]= low ) no lock ed ([ld]= high ) address2 write
[ak15 90 ] ms1478 - e - 01 19 20 13 / 2 6 . reference input the reference input can be set with a dividing number in the range of 4 to 255 using {r[7 :0]} , which is a 8 - bit address in . a dividing number from 0 to 3 cannot be set. 7 . prescaler and swallow counter the dual modul us prescaler (p/p+ 1) and the swallow counter are used to provide a large dividing ratio. the prescaler is set by {pre[1:0]} , which is a 2 - bit address in . when {pre[1:0]} =00 , p = 4 is selec ted and then an integer from 89 to 8191 can be set. when {pre[1:0]} =01, p = 8 is selected and then an integer from 201 to 16383 can be set. when {pre[1:0]} =10 or 11, p = 16 is selected and then an integer from 521 to 32767 can be set. for details of how to calculate an integer, see the section frequency setup in 8. block functional description. 8 . operation mode ak 1590 can be opera ted in p ower d own or p ower s ave mode as necessary by using the external control pins [ pdn1 ] and [ pdn2 ] . ? power on see 13 . power - up sequence. ? normal operation pin name mode pdn1 pdn2 low low power d own m ode low high prohibited high low power s ave m ode ( note 1 and note 2) high high normal operation m ode note 1) register s setting c an be acceptable after 50 ? s from [ pdn1 ] is set to high . the charge pump is in hi - z state during this perio d . note 2) register s value are maintained when [ pdn2 ] is set to low during normal operation mode .
[ak15 90 ] ms1478 - e - 01 20 20 13 / 2 9. register map name d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address num 0 0 num [17] num [16] num [15] num [14] num [13] num [12] num [11] num [10] num [9] num [8] num [7] num [6] num [5] num [4] num [3] num [2] num [1] num [0] 0x01 int 0 0 cp1 [2] cp1 [1] cp1 [0] int [14] int [13] int [12] int [11] int [10] int [9] int [8] int [7] int [6] int [5] int [4] int [3] int [2] int [1] int [0] 0x02 div 0 0 0 0 cp hiz dith ldck sel[1] ldck sel[0] ld cp pola pre [1] pre [0] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x03 c p _fast 0 0 0 fast en cp2 [2] cp2 [1] cp2 [0] fast [12] fast [11] fast [10] fast [9] fast [8] fast [7] fast [6] fast [5] fast [4] fast [3] fast [2] fast [1] fast [0] 0x04 gpo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpo 2 gpo 1 0x05 offset 0 0 of st [17] ofst [16] ofst [15] ofst [14] ofst [13] ofst [12] ofst [11] ofst [10] ofst [9] ofst [8] ofst [7] ofst [6] ofst [5] ofst [4] ofst [3] ofst [2] ofst [1] ofst [0] 0x06 note 1) writing into address 0x01 is enabled when writing into address 0x02 is pe rformed. be sure to write into address 0x01 first and then address 0x02. note 2) t he initial register values are not defined just after [pdn1] releases ([pdn1] set to high ) . therefore , even after [ pdn1 ] is set to high , each bit value remains undefined . in order to set all register values , it is required to write the data in all addresses of the register . name data address num d19 to d0 0 0 0 1 int 0 0 1 0 div 0 0 1 1 cp_fast 0 1 0 0 gpo 0 1 0 1 offset 0 1 1 0
[ak15 90 ] ms1478 - e - 01 21 20 13 / 2 10. register functional description < address 1: num > d19 d18 d[17:0] address 0 0 num[17:0] 0001 note) writing into address 0x01 is enabled when wr iting into address 0x02 is performed. num[17:0] : set the numerator in 2s complementary representation. < address 2: int > d19 d18 d[17:15] d[14:0] address 0 0 cp1[2:0] int[14:0] 0010 cp1[2 :0] : set the current value for the charge pump in normal op eration (charge pump 1). charge pump 1 current is determined by the following formula: cp1_min = 0. 57 / resistance connected to [bias] pin charge pump 1 current = cp1_min ( { cp1 [2:0]} + 1) int[14:0] : set the integer. when {pre[1:0]} =00, p = 4 is sel ected and then an integer from 89 to 8191 can be set. when {pre[1:0]} =01, p = 8 is selected and then an integer from 201 to 16383 can be set. when {pre[1:0]} =10 or 11, p = 16 is selected and then an integer from 521 to 32767 can be set. d [ 17 : 15 ] charge pump 1 current [ ? 22k? 27k? 33k? 000 25.9 2 1.1 17.3 001 51.8 4 2.2 34.5 010 77.7 63.3 51.8 011 103.6 8 4.4 69.1 100 129.5 100 .6 86.4 101 155.5 12 6.7 103.6 110 181.4 147.8 120.9 111 207.3 16 8.9 138.2
[ak15 90 ] ms1478 - e - 01 22 20 13 / 2 < address 3: div > d19 d18 d17 d16 d15 d14 d[13:12] d11 d10 d[9:8] d[7:0] addres s 0 0 0 0 cphiz dith ldcksel[1:0] ld cppola pre[1:0] r [7:0] 0011 cphiz: select normal or tri - state for the cp1/cp2 output. d15 function remarks 0 charge pumps are activated use thi s setting for normal operation 1 tri - state note 1 ) note 1) the charge pump output is p ut in hi - z state. dith: select dithering on or off for a delta - sigma circuit. d14 function remarks 0 dith off low noise mode 1 dith on low spurious mode it is used to control the turning on or o ff for dithering to cancel cyclical noise. ldcksel[1:0] : set phase error values for lock detect . d13 d12 function remarks 0 0 1 cycle of the refin clock 0 1 2 cycles of the refin clock 1 0 3 cycles of the refin clock 1 1 prohibited for detailed functional descriptions, see the section lock detect (ld) signal in 8 . block functional description. ld: select analog or digital for the lock detect. d11 function remarks 0 digital lock detect 1 analog lock detect for detailed functional descriptions, see the section lock detect (ld) signal in 8 . block functional description. cppola: select positive or negative output pola rity for charge pump 1 and charge pump 2. d10 function remarks 0 positive 1 negative
[ak15 90 ] ms1478 - e - 01 23 20 13 / 2 fig. 11 charge pump slope polarity pre[1:0] : select a dividing ratio for the prescaler. d9 d8 function remarks 0 0 p= 4 0 1 p=8 1 0 p=16 1 1 p=16 r[7:0]: set a dividing ratio for the reference clock. this can be set in the range from 4 (4 divisions) to 255 (255 divisions). 0 to 3 cannot be set. d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 p rohibited 0 0 0 0 0 0 0 1 1 prohibited 0 0 0 0 0 0 1 0 2 prohibited 0 0 0 0 0 0 1 1 3 prohibited data 1 1 1 1 1 1 0 1 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 high high charge pump output voltage negative positive low low vco frequency
[ak15 90 ] ms1478 - e - 01 24 20 13 / 2 < address 4: cp_fast > d19 d18 d17 d16 d[15:13] d[12:0] addres s 0 0 0 fasten c p2[2:0] fast[12:0] 0100 fasten: enable or disables the fast lockup mode. d16 function remarks 0 the switchover settings specified in cp2[2:0] and fast[12:0] are disabled. 1 the switchover settings specified in cp2[2:0] and fast[12:0] are enabled. cp2[2:0]: set the current value for the charge pump for the fast lockup mode (charge pump 2). charge pump 2 current is determined by the following formula: cp2_min = 5. 7 / resistance connected to [ bias ] pin charge pump 2 current = cp2_min ( { cp 2 [2: 0]} + 4) [ma] d [ 15 : 13 ] charge pump 2 current [ m a] 22k? 27k? 33k? 000 1.04 0.84 0.69 001 1.30 1.06 0.86 010 1.55 1.27 1.04 011 1.81 1.48 1.21 100 2.07 1.69 1.38 101 2.33 1.90 1.55 110 2.59 2.11 1.73 111 2.85 2.32 1.90
[ak15 90 ] ms1478 - e - 01 25 20 13 / 2 fast[12:0] : set the fast counter value. a decimal number from 1 to 8191 can b e set. this counter value is used to set the time period during which the charge pump for the fast lockup mode is on. the charge pump for the fast lockup mode is turned off after the time period calculated by this count value the reference clock cyc le . 0 cannot be set. d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 2 data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 1 1 1 1 1 1 1 1 1 1 1 1 1 8191
[ak15 90 ] ms1478 - e - 01 26 20 13 / 2 < address 5: gpo > d [19:2] d 1 d 0 address 0 gpo2 gpo1 01 01 gpo2: set the state of [ gpo2 ] pin t his value controls the general - p urpose o utput pin gpo2. the voltage applied to pvdd pin determines the high output level . d1 function remarks 0 low output from the gpo2 pin high output from the gpo2 pin gpo1: s et the state of [ gpo 1] pin this value controls the general - purpose o utput pin gpo1. the voltage applied to the pvdd pin determines the high output level . d0 function remarks 0 low output from the gpo1 pin high output from the gpo1 pin < address 6 : offset > d19 d18 d[17:0] address 0 0 ofst[17:0] 0110 ofst[17:0] : set the adjustable frequency offset in 2s complementary representation. this r egister designates offset from carrier frequency. after this register is accessed, {num[17:0]} and {int[14:0]} are recalculated and t hese recalculated data are used in delta - sigma and n - divider. when this register is not used, this register must be written 00000 (hexadecimal). offset register must be written at the lower speed than calculated frequency by 1/3.5 ? rf frequency /(int+7) . if the writing speed is f aster than this, the setting is in valid.
[ak15 90 ] ms1478 - e - 01 27 20 13 / 2 11. ic interface schematic no. n ame i/o r0( ? ) cur( ? a) function 4 le i 300 digital input pins 5 data i 300 6 clk i 300 8 pdn2 i 300 9 pdn1 i 300 2 test3 i 300 digital input pins pull - down 3 test1 i 300 11 test2 i 300 7 ld o digit al output pin 12 gpo1 o 13 gpo2 o 10 refin i 300 analog input pin 15 vref io 300 analog i/o pin 19 bias io 300 22 cpz io 300 r0 r0 100k r0 r0
[ak15 90 ] ms1478 - e - 01 28 20 13 / 2 no. n ame i/o r0( ? ) cur( ? a) function 23 swin i analog input pin 21 cp o analog output pin 16 rfinn i 40k 20 analog input pin ( rf signal input) 17 rfinp i 40k 20 r0
[ak15 90 ] ms1478 - e - 01 29 20 13 / 2 12. recommended con nection schematic for off - chip component s 1. pvdd , cpvdd 2. vref 3. test [1,2,3 ] pvdd cpvdd lsi 100p f 10 ? f 0.01 ? f 0.01 ? f 100p f 10 ? f vref vref2 lsi 220nf 10% test [ 1,2,3 ] lsi
[ak15 90 ] ms1478 - e - 01 30 20 13 / 2 4. refin 5. rfinp , rfinn 6. bias ref in lsi 100pf 10 % lsi rfinp vco output rfinn 100pf 10 % 100pf 10 % 5 1 lsi bias 22k ~33k
[ak15 90 ] ms1478 - e - 01 31 20 13 / 2 13. power - up sequence fig. 12 recommended power - up sequence note 1) the initial register values are not defined. therefore, even after [pdn1] is set to high, each bit value r emains undefined. in order to set all register values, it is required to write the data in all addresses of the register. note 2 ) it is prohibited to do power up and [pdn2] release at the same time. it is mandatory to power up first, then set [pdn2] to h igh . if they are set simultaneously, initial operation might be unstable. pdn1 write to the register on - chip ldo pdn2 th e register can be writte n internal register values are set cp output off on 50 ? s hi - z
[ak15 90 ] ms1478 - e - 01 32 20 13 / 2 14. typical evaluation board schematic fig. 13 typical evaluation board schematic the input voltage from [cpz] pin is us ed in the internal circuit. [ cpz] pin must not be open even when the f ast l ockup feature is unused. for the output destination from [cpz] pin, see fi g.5 loop filter schematic. [swin] pin could be open when the f ast l ockup feature is not used. r2 and r2 are conn ected in parallel with internal switch in fast lockup. these r2 and r2 parallel resistance value is required for calculating loop bandwidth and phase margin in fast lockup. the o n - resistance value of the internal switch is 150 ? for reference. it is recommended to connect the exposed pad (the center of the back of the package) to ground, although it will not make any impact on the electrical characteristics even if the pad is open. moreover, all test pins should be connected t o ground. c2 AK1590 loop filter c1 c3 r2 r2' r3 cp cpz swin rfout 51 ? 100pf rfinn vco bias rfinp 100pf 27k ? refin vref 220nf 100pf 100pf 18 ? 18 ? 18 ?
[ak15 90 ] ms1478 - e - 01 33 20 13 / 2 15. block diagram by power supply fig. 14 block diagram by power supply charge pump 2 (for fast lock up) cp cpz phase freqency detector refin + - prescaler 4/5, 8/9,16/17 pulse swallow counter lo ck detect rfinp rfinn swin cpvdd cpvss pvdd vref dvss pvss ld ? 18bit clk data le register 24bit n divider fast counter 13bit gpo1 test2 test1 ldo test3 gpo2 r counter 8bit bias charge pump 1 pdn1 pdn2 num offset + int sum pvdd cpvdd
[ak15 90 ] ms1478 - e - 01 34 20 13 / 2 16. outer dimensions fig. 15 outer dimensions no te) it is recommended to connect the exposed pad ( the center of the back of the package ) to ground, although it will not make any impact on the electrical characteristics eve if the pad is open. 0.05 s 2.40 2.40 0.400. 07 c0.30 1 13 18 19 24 12 7 4.000. 07 4.000. 07 0.220.05 a 2.00 b 2.0 0 s part a 0.5 0.75max 0.70 0.05max 6 0.05 m s a b 0.00 ~ 0.05 0.12 ~ 0.18 0.17 ~ 0.27 detailed chart in part a
[ak15 90 ] ms1478 - e - 01 35 20 13 / 2 17. marking (a) style : qfn (b) number of pins : 24 (c) 1 pin marking: : (d) product number : 1590 (e) date code : ywwl (4 digits) y : lower 1 d igit of calendar year (year 20 1 2 2 , 20 1 3 3 ...) ww : week l : lot identification, given to each product lot which is made in a week ? lot id is given in alphabetical order (a, b, c) . fig. 16 marking ywwl (e) (c) 1590 (d)
[ak15 90 ] ms1478 - e - 01 36 20 13 / 2 im portant notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document (product) , please make inquiries the sales office of akm or authorized distributors as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products. akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained i n this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in y our product design or applications. akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equip ment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equ ipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing. 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the pr oduct could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purpose s, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the pro duct. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring a s a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever, any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm.

▲Up To Search▲

Price & Availability of AK1590

	To Download AK1590 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .